With the rapid increment of integration and operating frequency of integrated circuits (ICs), the size of the IC must shrunk to meet the requirements of the semiconductor industry. A source/drain extension, a gate length, and junction depth of the source/drain particularly need to be diminished to solve the problems of process complexity and severe short channel effects.
To solve the problem of the short channel effects, a junction depth reduction of the source/drain extension has been developed. FIG. 1 shows a cross-sectional view of a conventional MOSFET. A source/drain 102 is formed on a substrate 100 and a channel region 104 is located between the source and the drain 102. Additionally, a source/drain extension 106 is positioned between the source/drain 102 and the channel region 104, and a spacer 112 is located above the source/drain extension 106. A gate oxide layer 108 and a gate 110 are deposited on the channel region 104.
However, doping concentration and junction depth of the source/drain extension 106 are lower and shallower, respectively, than those of the source/drain 102, which lead to worse performance of the MOSFET when the gate is turned on. Moreover, for techniques below 0.1 μm, the junction depth of the source/drain 106 must to be lower than 330 angstroms or much less. Therefore, to obtain a shallow junction depth in the source/drain extension 106, many doping and annealing steps tightly controlled bring additional cost and complexity during processing.
Consequently, how to improve device performance due to a high resistance in the source/drain extension is an important problem and is currently a main issue for semiconductor manufacturers.